Inside Intel’s Strategy to Integrate Nervana Deep Learning Assets

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April 19, 2017 | Originally published by Date Line: April 19 on

There is little doubt that 2017 will be a dense year for deep learning. With a sudden new wave of applications that integrate neural networks into existing workflows (not to mention entirely new uses) and a fresh array of hardware architectures to meet them, we expect the space to start shaking out its early winners and losers and show a clearer path ahead.

As we described earlier this week, Intel has big plans to integrate the Nervana ASIC and software stack with its Knights family of processors in the next several years. This effort, codenamed Knights Crest, is a long-term initiative, backed by numerous investments as early as 2017 with the roll-out of a 28nm process Nervana chip fabbed at TSMC and set to follow the original plans that the company’s former CEO (now head of the AI Solutions Group at Intel), Naveen Rao, told us about back in August 2016 immediately after the Intel acquisition announcement. At that time, Rao pointed to a strategy that VP and GM of the Xeon and Cloud Platforms group at Intel, Jason Waxman, told us this week they will be sticking by in the coming year and beyond.

As Rao said in August, “in the future, we would love to get access to the better 14 nm process technologies. As a startup, we had to use the most basic, bare-bones thing possible. But even with inferior process technology it is possible to beat a more general purpose processor.” Additionally, with the capabilities of 3D-Xpoint memory, what this tiny chip can do for deep learning (deeper piece on the architecture here) could be nothing short of incredible, assuming the workload doesn’t change significantly in the years required to get to this level of integration.