Researchers have built and demonstrated a novel configurable computing device that uses a thousand times less electrical power – and can be built up to a hundred times smaller – than comparable digital floating-gate configurable devices currently in use.
The new device, called the Field-Programmable Analog Array (FPAA) System-On-Chip (SoC), uses analog technology supported by digital components to achieve unprecedented power and size reductions. The researchers said that for many applications these low-power analog-based chips are likely to work as well as or better than configurable digital arrays.
Currently, field programmable gate arrays (FPGAs) – digital devices widely used in consumer devices, defense systems and more – dominate the configurable chip market. These floating-gate integrated circuits can be altered internally at any time, and techniques to reconfigure them for many different forms and functions are well established.
Professionals familiar with FPGAs will find the programming interface of the new analog chip surprisingly like the digital circuits in many ways, said Jennifer Hasler, a professor in the Georgia Tech School of Electrical and Computer Engineering (ECE) and leader of the research team that produced the new analog architecture.
“But in other ways the FPAA is going to seem quite different,” she said. “In terms of the power needed, it”s extremely different because you need only milliwatts to run the analog device, while it’s hard to get an FPGA to work on less than a watt.”